In multi-ported internally cached dynamically accessed memory systems (AMPIC devices)--a new paradigm in shared memory core switching described in said co-pending application and hereinafter more tully explained,--independent serial interface cache data is written into the AMPIC device before writing it into shared internal DRAM banks, over which contention arises. The caching of the data received on the serial interfaces reduces the chances that internal contention to a particular DRAM bank will affect the overall external performance of the serial interfaces by increasing the number of requests that may be outstanding to a particular internal AMPIC DRAM bank before it becomes necessary to stop the writing of information on one of the external serial interfaces in order to avoid overrunning the limited write cache space for the particular serial interface. Because of the potential for a large number of read and write access requests to be contending for a particular DRAM bank, the time it takes the AMPIC device to write data into one of the internal DRAM banks can significantly vary up to some finite maximum amount of time. If data is written to a particular address in one of the internal DRAM banks within the AMPIC and that same address is requested before the written data moves from the write cache into the actual DRAM bank location specified by the address, the old data (or stale data) currently stored at that address will be returned instead of the newly written data in the event that the read access to the DRAM bank should be granted before the write access.
Thus, it is desirable to have a method of guaranteeing that a read operation to a specific internal DRAM bank address returns the data that was last written to that particular address prior to the read operation; or to provide some means of returning information to the logic that generated the read request, stating that the data at the requested AMPIC device address is not up to date. The present invention addresses this need by novel data validation methods that thus enhance the performance and cache coherency of the AMPIC switching architecture.
In other types of digital systems, data validation mechanisms are used for microprocessor caching and for networking data transmission validation, but these mechanisms differ greatly in purpose and in implementation from the invention described in the present application for use with the AMPIC technology.
Designers of microprocessors have used memory caching techniques for some time, for example, to ease the bottleneck in processor performance between a processor and its memory. Basically, the processor keeps duplicate copies of smaller sections of what is in the main memory in a faster caching memory to improve performance. There is, however, the problem of keeping the duplicate copies of data up-to-date, or having the same value. Most caching algorithms focus on ensuring that when data is changed in the cache, the corresponding data in main memory is immediately updated (caching write-through schemes), or is marked as needing to be updated in the future ("dirty bit" caching schemes). This memory validation problem is much different from the data switching problem of the present invention in that one source, the microprocessor, controls the contents of the cache that it uses for main memory. For the AMPIC technology, of the invention, on the other hand, there are many sources and many caches that are controlled independently of one another and all used in conjunction to keep the data in the DRAM banks of the AMPIC devices up to date. Solving the problem of having many sources and caches for the AMPIC technology is therefore very different from the microprocessor caching techniques that have heretofore been developed for microprocessors.
Another area in which validation schemes have been previously used is in data link protocols for the transmission of data from a source to a destination in networking. These protocols are used to guarantee that the data received is actually the data sent. Most of these protocols allow only a limited number of packets to be transmitted until the receiver acknowledges correct reception of the packets. By including a sequence number, these protocols allow the receive side to identify the last correct packet that it received, indicating on which packet the transmitter should start sending again. By limiting the number of packets that the transmitter can have outstanding at one time to be less than the number of packets that can be identified by the sequence number, it can be guaranteed that both the transmitter and receiver can communicate which packets were lost and which need to be retransmitted. The most common of these data link layers is the "sliding window" protocol described, for example, in COMPUTER NETWORKS, 2.sup.nd Edition, by Andrew S. Tanenbaum; pages 212-228, using such sequence numbers. While these data link protocols are designed to determine when packets were transmitted incorrectly from one to another across noisy data communication lines, they are not applicable to the validating of data retrieved from an AMPIC DRAM memory and the race condition that makes the validation scheme of the present invention, necessary. In the sliding window protocol moreover, the receiver passively waits to receive the next packets and determines what to do next when the packet comes in with its sequence number.
Quite differently, in the present invention, data is placed in AMPIC devices, informing the destination of the existence of this data, and enabling the destination then actively to fetch the data. In this invention, furthermore, specialized logic is provided in the AMPIC devices themselves to ensure that only valid data or appropriately marked invalid data is transmitted back to the destination source.